The present invention relates to memory systems, and more specifically, to a memory system with a programmable refresh cycle.
As processor speeds continue to increase, memory performance becomes more of a limiting factor in system performance and therefore, memory performance must increase as well. An important aspect of increasing memory performance is increasing the throughput of memory systems. Some memory devices, such as direct random access memory (DRAM) devices require periodic refreshing of their memory cells to prevent data loss. In order to perform a refresh, a memory device enters a refresh mode where the DRAM is not accessible until the refresh has completed execution.
Memory controllers issue refresh commands on a periodic basis so that all memory cells in a DRAM device are refreshed at least once in every predetermined refresh period. The length of the refresh period is dictated by the memory device specifications, with a typical DRAM memory cell requiring a refresh every sixty four milliseconds (64 ms). The number of memory cells refreshed in a single refresh operation is typically fixed and determined by both the total number of cells in the memory device and the total number of refresh commands issued in each refresh period (referred to as a refresh interval). For example, if a memory device having eight thousand bits (8 Kbits) and a refresh period of 64 ms may have a refresh interval of 7.8 microseconds (mμ) and will refresh one bit during a single refresh cycle (64 ms/8192 bits=7.8 mμ. The number of refreshed cells per refresh cycle increases proportionally to the device density. For example, in a one gigabit (1 Gbit) memory device having a refresh period of 64 ms and a refresh interval of 7.8 mμ, 128 Kbits are refreshed in one refresh cycle. For a 2 Gbit memory device, having a refresh period of 64 ms and a refresh interval of 7.8 mμ, 256 Kbits are refreshed in one refresh cycle (twice as many as during a refresh interval in a 1 Gbit memory device).
The DRAM is not accessible when it is executing the refresh command because typically the banks are refreshed at the same time so there is no available bank for normal access during the refresh period. The memory controller waits until the internal refresh operation has completed before resuming normal operation (e.g., before sending another command such as a read or write command). This period of time when the DRAM is not accessible is referred to as lockout time. The lockout time is equal to the delay required between two back-to-back refresh commands (referred to the minimum refresh cycle time or tRFC).
A drawback of higher density memory devices is that the lockout time increases as more and more cells require refreshing during each refresh cycle. Another drawback is that more noise is generated when more cells are being refreshed in the same cycle. As described previously, an increase in the amount of lockout time required for completing refresh operations has a direct impact on memory system throughput.
Accordingly, and while existing memory systems may be suitable for their intended purposes, there remains a need in the art for memory systems that overcome these drawbacks for high density memory devices.